A Third-Order MASH Σ Δ Modulator Using Passive Integrators

Blazej Nowacki, Nuno Paulino, Joao Goes

Research output: Contribution to journalArticlepeer-review

10 Citations (Scopus)

Abstract

This paper presents a MASHΣ Δ M using only passive integrators and simple differential pairs as low-gain blocks. Instead of high-gain power hungry op-amps it uses more processing gain from the comparator (1-bit quantizer) as a part of the loop gain. The proposed approach allows the design of a continuous-time, 2-1 MASH Σ ΔM}in a 65-nm CMOS technology occupying an area of just 0.027 mm2. Measurement results show that the modulator achieves a peak SNR/SNDR of 76/72.2 dB and a DR of 77 dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW with 1 V supply. The proposed Σ ΔM achieves a Walden figures of merit (FoM) of 23.6 fJ/level and a Schreier FOM of 170 dB.

Original languageEnglish
Article number7935461
Pages (from-to)2871-2883
Number of pages13
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume64
Issue number11
DOIs
Publication statusPublished - 1 Nov 2017

Keywords

  • continuous-time
  • CT mash
  • mash
  • oversampling
  • passive integrator
  • Sigma-delta modulation

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