A Simple Analysis to Determine the Limits of a CMOS Technology to Implement SC DC-DC Converters

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a simple analysis that allows to determine the maximum power density and efficiency of a SC DC-DC converter for a given CMOS technology. By determining the values of the ratio between the switches’ gate capacitance and channel width, and between the ON resistance and the channel width, together with the parasitic capacitances from the flying capacitors, it is possible to plot the efficiency as a function of the power density for a given input and output voltage of the converter, allowing to quickly determine both the expected efficiency and clock frequency ranges of the converter, for a given CMOS technology.

Original languageEnglish
Title of host publicationTechnological Innovation for Life Improvement - 11th IFIP WG 5.5/SOCOLNET Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2020, Proceedings
EditorsLuis M. Camarinha-Matos, Nastaran Farhadi, Fábio Lopes, Helena Pereira
Place of PublicationCham
PublisherSpringer
Pages265-273
Number of pages9
ISBN (Electronic)978-3-030-45124-0
ISBN (Print)978-3-030-45123-3
DOIs
Publication statusPublished - 2020
Event11th Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2020 - Costa de Caparica, Portugal
Duration: 1 Jul 20203 Jul 2020

Publication series

NameIFIP Advances in Information and Communication Technology
PublisherSpringer
Volume577
ISSN (Print)1868-4238
ISSN (Electronic)1868-422X

Conference

Conference11th Advanced Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2020
CountryPortugal
CityCosta de Caparica
Period1/07/203/07/20

Keywords

  • Design techniques
  • Power Management Unit
  • Switched-capacitor (SC) converter

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