A simple 1 GHz non-overlapping two-phase clock generators for SC circuit

This paper addresses the problem of generating non-overlapping clock phases for switched capacitor circuits at more than 1 GHz clock frequency. A simple clock phase generator providing two non-overlapping phases with low values of RMS period jitter, RMS jitter of phases' widths and phase shift of 180 degrees is proposed. The circuit relies on a back-to-back inverter structure. Simulation results over PVT corners (for non-ideal differential and single ended input clock signals) prove the effectiveness of the new circuit, which dissipates less power than the conventional NAND-based structure.