A simple 1 GHz non-overlapping two-phase clock generators for SC circuit

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

10 Citations (Scopus)

Abstract

This paper addresses the problem of generating non-overlapping clock phases for switched capacitor circuits at more than 1 GHz clock frequency. A simple clock phase generator providing two non-overlapping phases with low values of RMS period jitter, RMS jitter of phases' widths and phase shift of 180 degrees is proposed. The circuit relies on a back-to-back inverter structure. Simulation results over PVT corners (for non-ideal differential and single ended input clock signals) prove the effectiveness of the new circuit, which dissipates less power than the conventional NAND-based structure.
Original languageUnknown
Title of host publicationProceedings of the 20th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES 2013)
Pages174-178
Publication statusPublished - 1 Jan 2013
EventMIXDES 2013: 20th International Conference on Mixed Design of Integrated Circuits and Systems -
Duration: 1 Jan 2013 → …

Conference

ConferenceMIXDES 2013: 20th International Conference on Mixed Design of Integrated Circuits and Systems
Period1/01/13 → …

Cite this