his paper proposes a robust, 3-stage fully-dynamic high-gain residue amplifier for a 12-bit 80 MS/s two-stage SAR assisted pipeline ADC. Parametric amplification has been used in the proposed open-loop amplifier to enhance gain. Third stage of the circuit is implemented with dynamic source followers (DSFs), which contributed to gain enhancement and also promised a robust performance against different loads and process corners. The circuit has shown a gain of 31 dB, a power consumption of 0.1mW and an operating frequency of approximately 1 GHz from simulations. Circuit corner performance is varying almost within +/- 1 dB in gain and +/- 20% in bandwidth from the nominal. Circuit simulations have been carried out in standard 65 nm CMOS technology with a power supply of 1V.
|Journal||2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)|
|Publication status||Published - 2017|
- Integrated circuit modeling
- Power demand
- Logic gates