This paper proposes a new design for a Polyphase implementation of a third-order SINC filter (SINC3) with a decimation factor of 8. In order to make our solution more power efficient in comparison with the classical Polyphase filters, we use the counterclockwise commutator technique and, by applying a multiplexer interlaying strategy, we are able to implement a multiplier-free Polyphase structure. Moreover, by using properly defined control signals, our circuit takes advantage of dispatching input bit stream and navigating bits in the related sub-filters. High-level simulation results in MATLAB shows that our filter allows reaching a dynamic performance comparable to the ideal SINC3filter and, the corresponding implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution. The proposed new filter architecture can be readily applicable to any Sigma-Delta ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with state-of-the-art approaches.
|Title of host publication||International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)|
|Publication status||Published - 1 Jan 2011|
|Event||Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 - |
Duration: 1 Jan 2011 → …
|Conference||Mixed Design of Integrated Circuits and Systems (MIXDES), 2011|
|Period||1/01/11 → …|
Gomes, L. F. D. S., Goes, J. C. D. P., & Paulino, N. F. S. V. (2011). A polyphase comb filter using interlaying multiplexers for high-speed single-bit sigma-delta modulators. In International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) (pp. 216-220) http://www.scopus.com/inward/record.url?partnerID=yv4JPVwI&eid=2-s2.0-80053303696&md5=fe69e2dfd6c4d88bf6aa6ca17b7ca817