Abstract
In this paper a novel and mismatch-insensitive 1.5-bit MDAC is proposed. This circuit combines three main techniques that lead to a simulated reduction of the power dissipation of the order of 4 times, when compared to the conventional 1.5-bit MDAC circuit. Simulations also have shown that the proposed 1.5-bit MDAC is capable of achieving an SNDR of around 74 dB, i.e. compatible with 12 bits, corresponding to a 25 dB (4 bits) improvement when compared to the classic 1.5-bit MDAC. It is worth noticing that these results are achieved with a low gain, poor linearity and noisy residue amplifier, as all these innacuracies are cancelled thanks to the techniques employed.
Original language | English |
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Title of host publication | 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 |
Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
Pages | 375-378 |
Number of pages | 4 |
ISBN (Electronic) | 978-1-4799-4242-8 |
DOIs | |
Publication status | Published - 25 Feb 2015 |
Event | 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 - Marseille, France Duration: 7 Dec 2014 → 10 Dec 2014 |
Conference
Conference | 2014 21st IEEE International Conference on Electronics, Circuits and Systems, ICECS 2014 |
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Country/Territory | France |
City | Marseille |
Period | 7/12/14 → 10/12/14 |
Keywords
- lossless bottom-plate sampling
- Mismatch-Insensitive
- Pipeline ADCs
- Unity feedback-factor