A multi-cell SC DC-DC converter controller with power aware output ripple reduction

Ricardo Madeira; Joao P. Oliveira; Nuno Paulino

doi:10.1109/PRIME.2016.7519507

A multi-cell SC DC-DC converter controller with power aware output ripple reduction

Ricardo Madeira, Joao P. Oliveira, Nuno Paulino

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Citation (Scopus)

Abstract

This paper describes a method for reducing the output voltage ripple of a SC DC-DC converter. In a SC converter the clock frequency is proportional to the output power, meaning that for low power levels the resulting low frequency value translates into a large output voltage ripple. Since the clock frequency is inversely proportional to the flying capacitance value, it is possible to reduce the output voltage ripple by decreasing the flying capacitance when the output power is small. An asynchronous controller, uses the clock period to add or subtract capacitors (multi-cell) to the flying capacitance, maintaining a low ripple voltage. Simulation results show that this technique reduces the output voltage ripple by 6.2 times in the worst case, when compared to a single-cell converter, without any significant decrease in the overall efficiency.

Original language	English
Title of host publication	2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)	978-150900493-5
DOIs	https://doi.org/10.1109/PRIME.2016.7519507
Publication status	Published - 22 Jul 2016
Event	12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016 - Lisbon, Portugal Duration: 27 Jun 2016 → 30 Jun 2016

Conference

Conference	12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016
Country/Territory	Portugal
City	Lisbon
Period	27/06/16 → 30/06/16

Keywords

Capacitance
Clocks
Electric inverters
Microelectronics
Power management

Access to Document

10.1109/PRIME.2016.7519507Licence: Unspecified

Cite this

@inproceedings{eae41f848d134ea684d821bea67f4f54,

title = "A multi-cell SC DC-DC converter controller with power aware output ripple reduction",

abstract = "This paper describes a method for reducing the output voltage ripple of a SC DC-DC converter. In a SC converter the clock frequency is proportional to the output power, meaning that for low power levels the resulting low frequency value translates into a large output voltage ripple. Since the clock frequency is inversely proportional to the flying capacitance value, it is possible to reduce the output voltage ripple by decreasing the flying capacitance when the output power is small. An asynchronous controller, uses the clock period to add or subtract capacitors (multi-cell) to the flying capacitance, maintaining a low ripple voltage. Simulation results show that this technique reduces the output voltage ripple by 6.2 times in the worst case, when compared to a single-cell converter, without any significant decrease in the overall efficiency.",

keywords = "Capacitance, Clocks, Electric inverters, Microelectronics, Power management",

author = "Ricardo Madeira and Oliveira, {Joao P.} and Nuno Paulino",

note = "Sem PDF; 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016 ; Conference date: 27-06-2016 Through 30-06-2016",

year = "2016",

month = jul,

day = "22",

doi = "10.1109/PRIME.2016.7519507",

language = "English",

booktitle = "2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

Madeira, R, Oliveira, JP & Paulino, N 2016, A multi-cell SC DC-DC converter controller with power aware output ripple reduction. in 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016., 7519507, Institute of Electrical and Electronics Engineers (IEEE), 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016, Lisbon, Portugal, 27/06/16. https://doi.org/10.1109/PRIME.2016.7519507

A multi-cell SC DC-DC converter controller with power aware output ripple reduction. / Madeira, Ricardo; Oliveira, Joao P.; Paulino, Nuno.
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016. Institute of Electrical and Electronics Engineers (IEEE), 2016. 7519507.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A multi-cell SC DC-DC converter controller with power aware output ripple reduction

AU - Madeira, Ricardo

AU - Oliveira, Joao P.

AU - Paulino, Nuno

N1 - Sem PDF

PY - 2016/7/22

Y1 - 2016/7/22

N2 - This paper describes a method for reducing the output voltage ripple of a SC DC-DC converter. In a SC converter the clock frequency is proportional to the output power, meaning that for low power levels the resulting low frequency value translates into a large output voltage ripple. Since the clock frequency is inversely proportional to the flying capacitance value, it is possible to reduce the output voltage ripple by decreasing the flying capacitance when the output power is small. An asynchronous controller, uses the clock period to add or subtract capacitors (multi-cell) to the flying capacitance, maintaining a low ripple voltage. Simulation results show that this technique reduces the output voltage ripple by 6.2 times in the worst case, when compared to a single-cell converter, without any significant decrease in the overall efficiency.

AB - This paper describes a method for reducing the output voltage ripple of a SC DC-DC converter. In a SC converter the clock frequency is proportional to the output power, meaning that for low power levels the resulting low frequency value translates into a large output voltage ripple. Since the clock frequency is inversely proportional to the flying capacitance value, it is possible to reduce the output voltage ripple by decreasing the flying capacitance when the output power is small. An asynchronous controller, uses the clock period to add or subtract capacitors (multi-cell) to the flying capacitance, maintaining a low ripple voltage. Simulation results show that this technique reduces the output voltage ripple by 6.2 times in the worst case, when compared to a single-cell converter, without any significant decrease in the overall efficiency.

KW - Capacitance

KW - Clocks

KW - Electric inverters

KW - Microelectronics

KW - Power management

UR - http://www.scopus.com/inward/record.url?scp=84992121876&partnerID=8YFLogxK

U2 - 10.1109/PRIME.2016.7519507

DO - 10.1109/PRIME.2016.7519507

M3 - Conference contribution

AN - SCOPUS:84992121876

BT - 2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016

Y2 - 27 June 2016 through 30 June 2016

ER -

A multi-cell SC DC-DC converter controller with power aware output ripple reduction

Abstract

Conference

Keywords

Access to Document

Other files and links

Fingerprint

Cite this