A multi-cell SC DC-DC converter controller with power aware output ripple reduction

Ricardo Madeira, Joao P. Oliveira, Nuno Paulino

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper describes a method for reducing the output voltage ripple of a SC DC-DC converter. In a SC converter the clock frequency is proportional to the output power, meaning that for low power levels the resulting low frequency value translates into a large output voltage ripple. Since the clock frequency is inversely proportional to the flying capacitance value, it is possible to reduce the output voltage ripple by decreasing the flying capacitance when the output power is small. An asynchronous controller, uses the clock period to add or subtract capacitors (multi-cell) to the flying capacitance, maintaining a low ripple voltage. Simulation results show that this technique reduces the output voltage ripple by 6.2 times in the worst case, when compared to a single-cell converter, without any significant decrease in the overall efficiency.

Original languageEnglish
Title of host publication2016 12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)978-150900493-5
DOIs
Publication statusPublished - 22 Jul 2016
Event12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016 - Lisbon, Portugal
Duration: 27 Jun 201630 Jun 2016

Conference

Conference12th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2016
CountryPortugal
CityLisbon
Period27/06/1630/06/16

Keywords

  • Capacitance
  • Clocks
  • Electric inverters
  • Microelectronics
  • Power management

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