A methodology for modelling and simulation of saturated cores fault current limiters

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19 Citations (Scopus)


Inductive fault current limiters, such as saturated cores topology, have been considered as an enabling technology for the advent of modern power grids. Thereby, several full-scale prototypes have been developed in recent years aiming e.g. supporting increased penetration of dispersed generation, mostly from renewable sources. For the advent of these devices and technology, the development of straightforward design tools that allow simulating them in electrical power grids with different voltage ratings and characteristics is required. In this paper, a methodology for simulating the behavior of saturated cores limiters is presented as an alternative to techniques based on finite elements methods (FEM), thereby dramatically reducing computation time. This methodology is based on characteristic parameters of those limiters and is compared with FEM simulations. Experimental measurements in a laboratory scale prototype are also carried out in order to validate the proposed methodology.
Original languageUnknown
Pages (from-to)1-1
JournalIeee Transactions On Applied Superconductivity
Issue number99
Publication statusPublished - 1 Jan 2014

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