This paper presents a new CMOS buffer circuit topology for radio-frequency (RF) applications based on a fully-differential voltage-combiner circuit, capable of operating at low-voltage. The proposed circuit uses a combination of common-source (CS) and common-drain (CD) devices. The simulation results show good levels of linearity and bandwidth. To improve total harmonic distortion (THD) a source degeneration technique is used. The proposed circuit has been designed in a 130nm logic CMOS technology and it achieves a simulated gain of 1.54 dB, a bandwidth of 1.14 GHz for a total power dissipation of 13.34 mW, when driving an RF active probe (with 0.8 pF in parallel with 200 kΩ).
|Title of host publication||IFIP Advances in Information and Communication Technology|
|Publication status||Published - 1 Jan 2013|
|Event||DoCEIS’13: 4th Doctoral Conference on Computing, Electrical and Industrial Systems - |
Duration: 1 Jan 2013 → …
|Conference||DoCEIS’13: 4th Doctoral Conference on Computing, Electrical and Industrial Systems|
|Period||1/01/13 → …|
Abdollahvand, S., Santos-tavares, R. M. L., & Goes, J. C. D. P. (2013). A Low-Voltage CMOS Buffer for RF Applications Based on a Fully-Differential Voltage-Combiner. In IFIP Advances in Information and Communication Technology (pp. 611-618). [A067] https://doi.org/10.1007/978-3-642-37291-9_66