A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling

Blazej Nowacki; Nuno Filipe Silva Veríssimo Paulino; João Carlos da Palma Goes

doi:10.1109/ISCAS.2014.6865392

A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling

Blazej Nowacki, Nuno Filipe Silva Veríssimo Paulino, João Carlos da Palma Goes

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Citations (Scopus)

Abstract

A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.

Original language	English
Title of host publication	2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages	1344 - 1347
ISBN (Electronic)	978-1-4799-3432-4
DOIs	https://doi.org/10.1109/ISCAS.2014.6865392
Publication status	Published - 2014
Event	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 - Melbourne, VIC, Australia Duration: 1 Jun 2014 → 5 Jun 2014

Conference

Conference	2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014
Country/Territory	Australia
City	Melbourne, VIC
Period	1/06/14 → 5/06/14

Keywords

analog-to-digital (A/D) conversion
Cascaded delta-sigma modulator
MASH
passive integrator
passive SC filter

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10.1109/ISCAS.2014.6865392

Cite this

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title = "A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling",

abstract = "A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.",

keywords = "analog-to-digital (A/D) conversion, Cascaded delta-sigma modulator, passive SC filter, passive integrator, MASH, analog-to-digital (A/D) conversion, Cascaded delta-sigma modulator, MASH, passive integrator, passive SC filter",

author = "Blazej Nowacki and Paulino, \{Nuno Filipe Silva Ver{\'i}ssimo\} and Goes, \{Jo{\~a}o Carlos da Palma\}",

year = "2014",

doi = "10.1109/ISCAS.2014.6865392",

language = "English",

isbn = "978-1-4799-3431-7",

pages = "1344 -- 1347",

booktitle = "2014 IEEE International Symposium on Circuits and Systems (ISCAS)",

note = "2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014 ; Conference date: 01-06-2014 Through 05-06-2014",

}

Nowacki, B, Paulino, NFSV & Goes, JCDP 2014, A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling. in 2014 IEEE International Symposium on Circuits and Systems (ISCAS)., 6865392, pp. 1344 - 1347, 2014 IEEE International Symposium on Circuits and Systems, ISCAS 2014, Melbourne, VIC, Australia, 1/06/14. https://doi.org/10.1109/ISCAS.2014.6865392

A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling. / Nowacki, Blazej; Paulino, Nuno Filipe Silva Veríssimo ; Goes, João Carlos da Palma.
2014 IEEE International Symposium on Circuits and Systems (ISCAS). 2014. p. 1344 - 1347 6865392.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.

AB - A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.

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KW - passive integrator

KW - passive SC filter

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M3 - Conference contribution

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BT - 2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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ER -

A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling

Abstract

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Keywords

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