A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling

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4 Citations (Scopus)

Abstract

A discrete-time, switched-capacitor, MASH 2-2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth of 10 MHz, while dissipating 1.5 mW from a 1.1 V power supply voltage, indicating that, a FOM of 42.7 fJ/conv.-step can be reached.
Original languageEnglish
Title of host publication2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Pages1344 - 1347
ISBN (Electronic)978-1-4799-3432-4
DOIs
Publication statusPublished - 2014
Event2014 IEEE International Symposium on Circuits and Systems (ISCAS) -
Duration: 1 Jan 2014 → …

Conference

Conference2014 IEEE International Symposium on Circuits and Systems (ISCAS)
Period1/01/14 → …

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Keywords

  • analog-to-digital (A/D) conversion
  • Cascaded delta-sigma modulator
  • MASH
  • passive integrator
  • passive SC filter

Cite this

Nowacki, B., Paulino, N. F. S. V., & Goes, J. C. D. P. (2014). A low power 4th order MASH switched-capacitor ΣΔ modulator using ultra incomplete settling. In 2014 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1344 - 1347). [6865392] https://doi.org/10.1109/ISCAS.2014.6865392