TY - GEN
T1 - A Low Noise CMOS Inverter-Based OTA for and Healthcare Signal Receivers
AU - Póvoa, Ricardo
AU - Canelas, António
AU - Martins, Ricardo M. F.
AU - Horta, Nuno
AU - Lourenço, Nuno
AU - Goes, João
N1 - This work was supported in part by Fundação para a Ciência e Tecnologia under Grant SFRH/BD/103337/2014, Grant SFRH/BPD/104648/2014, Grant SFRH/BPD/120009/ 2016, and by Instituto de Telecomunicações under Research Project UID/EEA/50008/2019.
PY - 2019/7/1
Y1 - 2019/7/1
N2 - This paper presents an innovative topology for an operational transconductance amplifier (OTA) based on a CMOS inverter topology. This OTA is proper for biomedical and healthcare circuits and systems, due to a low level of noise and power consumption, together with elevated gain. This is a fully-differential implementation, with a double CMOS branch biased by two pairs of voltage-combiners, in both NMOS and PMOS configurations, highly improving the gain and the gain-bandwidth product, improving the OTA energy-efficiency. An elevated figure-of-merit is achieved, i.e., a 1628 MHz×pF/mA, and a gain of 53 dB, under a voltage supply source of 2 V. The results are compared with state-of-the-art OTAs in this field of study and the potential is fully fulfilled with a state-of-the-art layout-aware optimization tool, AIDA, particularly important to overcome the device stacking problematic in lower supplies.
AB - This paper presents an innovative topology for an operational transconductance amplifier (OTA) based on a CMOS inverter topology. This OTA is proper for biomedical and healthcare circuits and systems, due to a low level of noise and power consumption, together with elevated gain. This is a fully-differential implementation, with a double CMOS branch biased by two pairs of voltage-combiners, in both NMOS and PMOS configurations, highly improving the gain and the gain-bandwidth product, improving the OTA energy-efficiency. An elevated figure-of-merit is achieved, i.e., a 1628 MHz×pF/mA, and a gain of 53 dB, under a voltage supply source of 2 V. The results are compared with state-of-the-art OTAs in this field of study and the potential is fully fulfilled with a state-of-the-art layout-aware optimization tool, AIDA, particularly important to overcome the device stacking problematic in lower supplies.
KW - CMOS
KW - Differential
KW - Energy-Efficiency
KW - Inverter-Based
KW - Low-Current
KW - On-chip
KW - OTA
KW - Voltage-Combiners
UR - http://www.scopus.com/inward/record.url?scp=85071533627&partnerID=8YFLogxK
U2 - 10.1109/SMACD.2019.8795248
DO - 10.1109/SMACD.2019.8795248
M3 - Conference contribution
AN - SCOPUS:85071533627
T3 - International Conference on Synthesis Modeling Analysis and Simulation Methods and Applications to Circuit Design
SP - 161
EP - 164
BT - SMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedings
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2019
Y2 - 15 July 2019 through 18 July 2019
ER -
