A hybrid current-mode passive second-order continuous-time ΣΔ modulator

Pawel Sniatala, Mariusz Naumowicz, Joao L.A. de Melo, Nuno Filipe Silva Veríssimo Paulino, João Carlos da Palma Goes

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC.
Original languageEnglish
Title of host publicationMixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference
Pages117 - 120
ISBN (Electronic)978-83-63578-04-6
DOIs
Publication statusPublished - 2014
Event21st International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES) -
Duration: 1 Jan 2014 → …

Conference

Conference21st International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES)
Period1/01/14 → …

Fingerprint

Passive filters
Low pass filters
Modulators
Clocks
Electric power utilization
Topology
Bandwidth
Networks (circuits)

Keywords

  • Current-mode
  • Sigma-delta modulator

Cite this

Sniatala, P., Naumowicz, M., de Melo, J. L. A., Paulino, N. F. S. V., & Goes, J. C. D. P. (2014). A hybrid current-mode passive second-order continuous-time ΣΔ modulator. In Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference (pp. 117 - 120). [6872168] https://doi.org/10.1109/MIXDES.2014.6872168
Sniatala, Pawel ; Naumowicz, Mariusz ; de Melo, Joao L.A. ; Paulino, Nuno Filipe Silva Veríssimo ; Goes, João Carlos da Palma. / A hybrid current-mode passive second-order continuous-time ΣΔ modulator. Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference. 2014. pp. 117 - 120
@inproceedings{b4ee69c126de4b5bbea8d7a2fb067a9e,
title = "A hybrid current-mode passive second-order continuous-time ΣΔ modulator",
abstract = "This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC.",
keywords = "Current-Mode, Sigma-Delta Modulator, Current-mode, Sigma-delta modulator",
author = "Pawel Sniatala and Mariusz Naumowicz and {de Melo}, {Joao L.A.} and Paulino, {Nuno Filipe Silva Ver{\'i}ssimo} and Goes, {Jo{\~a}o Carlos da Palma}",
note = "This work was supported by the Portuguese Foundation for Science and Technology ( CTS multiannual funding) through the PIDDAC Program funds, projects DISRUPTIVE ( EXCL/ EEI- ELC/ 0261/ 2012) and PEST ( PEST- OE/ EEI/ UI0066/ 2011) and also through Ph. D. Grant ( SFRH/ BD/ 72362/ 2010).",
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Sniatala, P, Naumowicz, M, de Melo, JLA, Paulino, NFSV & Goes, JCDP 2014, A hybrid current-mode passive second-order continuous-time ΣΔ modulator. in Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference., 6872168, pp. 117 - 120, 21st International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES), 1/01/14. https://doi.org/10.1109/MIXDES.2014.6872168

A hybrid current-mode passive second-order continuous-time ΣΔ modulator. / Sniatala, Pawel; Naumowicz, Mariusz; de Melo, Joao L.A.; Paulino, Nuno Filipe Silva Veríssimo; Goes, João Carlos da Palma.

Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference. 2014. p. 117 - 120 6872168.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Sniatala, Pawel

AU - Naumowicz, Mariusz

AU - de Melo, Joao L.A.

AU - Paulino, Nuno Filipe Silva Veríssimo

AU - Goes, João Carlos da Palma

N1 - This work was supported by the Portuguese Foundation for Science and Technology ( CTS multiannual funding) through the PIDDAC Program funds, projects DISRUPTIVE ( EXCL/ EEI- ELC/ 0261/ 2012) and PEST ( PEST- OE/ EEI/ UI0066/ 2011) and also through Ph. D. Grant ( SFRH/ BD/ 72362/ 2010).

PY - 2014

Y1 - 2014

N2 - This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC.

AB - This paper describes the design of a current-mode, active-passive second-order, continuous-time Sigma-Delta Modulator(ΣΔM). The proposed ΣΔM uses a single continuous-time current-mode integrator combined with low-pass passive filter topology. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 400 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 60.7 dB and a dynamic range(DR) of 65 dB while dissipating 132 μW which corresponds to an efficiency of 37.3 fJ/conv. The proposed architecture allows to obtain the best compromise between power consumption and performance of the ADC.

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BT - Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference

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Sniatala P, Naumowicz M, de Melo JLA, Paulino NFSV, Goes JCDP. A hybrid current-mode passive second-order continuous-time ΣΔ modulator. In Mixed Design of Integrated Circuits & Systems (MIXDES), 2014 Proceedings of the 21st International Conference. 2014. p. 117 - 120. 6872168 https://doi.org/10.1109/MIXDES.2014.6872168