A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs

Pydi Ganga Bahubalindruni; João Goes; Pedro Barquinha

doi:10.1109/SMACD.2016.7520732

A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs

Pydi Ganga Bahubalindruni, João Goes, Pedro Barquinha

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Citations (Scopus)

Abstract

This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when V_DD is 1.2 V and C_L is 150 fF in a standard 65 nm CMOS technology.

Original language	English
Title of host publication	2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
ISBN (Electronic)	9781509004904
DOIs	https://doi.org/10.1109/SMACD.2016.7520732
Publication status	Published - 25 Jul 2016
Event	13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016 - Lisbon, Portugal Duration: 27 Jun 2016 → 30 Jun 2016

Conference

Conference	13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016
Country/Territory	Portugal
City	Lisbon
Period	27/06/16 → 30/06/16

Keywords

Parametric amplifier
Residue amplification
SAR-assisted pipeline ADC

Access to Document

10.1109/SMACD.2016.7520732Licence: Unspecified

Cite this

Bahubalindruni, P. G., Goes, J., & Barquinha, P. (2016). A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs. In 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016 Article 7520732 Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/SMACD.2016.7520732

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abstract = "This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.",

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Bahubalindruni, PG, Goes, J & Barquinha, P 2016, A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs. in 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016., 7520732, Institute of Electrical and Electronics Engineers (IEEE), 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016, Lisbon, Portugal, 27/06/16. https://doi.org/10.1109/SMACD.2016.7520732

A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs. / Bahubalindruni, Pydi Ganga; Goes, João ; Barquinha, Pedro.
2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016. Institute of Electrical and Electronics Engineers (IEEE), 2016. 7520732.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Bahubalindruni, Pydi Ganga

AU - Goes, João

AU - Barquinha, Pedro

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Y1 - 2016/7/25

N2 - This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.

AB - This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.

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Bahubalindruni PG, Goes J , Barquinha P. A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs. In 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016. Institute of Electrical and Electronics Engineers (IEEE). 2016. 7520732 doi: 10.1109/SMACD.2016.7520732

A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs

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