A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs

Pydi Ganga Bahubalindruni, João Goes, Pedro Barquinha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology.

Original languageEnglish
Title of host publication2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509004904
DOIs
Publication statusPublished - 25 Jul 2016
Event13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016 - Lisbon, Portugal
Duration: 27 Jun 201630 Jun 2016

Conference

Conference13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016
CountryPortugal
CityLisbon
Period27/06/1630/06/16

Keywords

  • Parametric amplifier
  • Residue amplification
  • SAR-assisted pipeline ADC

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