A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits

R. Póvoa; A. Canelas; R. Martins; N. Lourenço; N. Horta; J. Goes

doi:10.1109/PRIME.2017.7974122

A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits

R. Póvoa, A. Canelas, R. Martins, N. Lourenço, N. Horta, J. Goes

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mA_rms for a sampling clock frequency of 100MHz.

Original language	English
Title of host publication	PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	121-124
Number of pages	4
ISBN (Print)	978-1-5090-6508-0
DOIs	https://doi.org/10.1109/PRIME.2017.7974122
Publication status	Published - 10 Jul 2017
Event	13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 - Giardini Naxos - Taormina, Italy Duration: 12 Jun 2017 → 15 Jun 2017

Conference

Conference	13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017
Country/Territory	Italy
City	Giardini Naxos - Taormina
Period	12/06/17 → 15/06/17

Keywords

Common-Drain
Common-Source
Design Automation
Digital Filters
Dynamic Amplifier
Energy-Efficiency
High-Speed Low-Power ADC
Switched-Capacitors
Voltage-Combiners

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/PRIME.2017.7974122

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Póvoa, R., Canelas, A., Martins, R., Lourenço, N., Horta, N., & Goes, J. (2017). A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits. In PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings (pp. 121-124). [7974122] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/PRIME.2017.7974122

@inproceedings{ac08bcc96b364803906834d846d85329,

title = "A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits",

abstract = "This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.",

keywords = "Common-Drain, Common-Source, Design Automation, Digital Filters, Dynamic Amplifier, Energy-Efficiency, High-Speed Low-Power ADC, Switched-Capacitors, Voltage-Combiners",

author = "R. P{\'o}voa and A. Canelas and R. Martins and N. Louren{\c c}o and N. Horta and J. Goes",

note = "Instituto de Telecomunicacoes: RAPID UID/EEA/50008/2013 ; FCT-SFRH/BD/103337/2014; SFRH/BPD/104648/2014.; 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 ; Conference date: 12-06-2017 Through 15-06-2017",

year = "2017",

month = jul,

day = "10",

doi = "10.1109/PRIME.2017.7974122",

language = "English",

isbn = "978-1-5090-6508-0",

pages = "121--124",

booktitle = "PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

address = "United States",

}

Póvoa, R, Canelas, A, Martins, R, Lourenço, N, Horta, N & Goes, J 2017, A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits. in PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings., 7974122, Institute of Electrical and Electronics Engineers Inc., pp. 121-124, 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017, Giardini Naxos - Taormina, Italy, 12/06/17. https://doi.org/10.1109/PRIME.2017.7974122

A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits. / Póvoa, R.; Canelas, A.; Martins, R.; Lourenço, N.; Horta, N.; Goes, J.

PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. p. 121-124 7974122.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits

AU - Póvoa, R.

AU - Canelas, A.

AU - Martins, R.

AU - Lourenço, N.

AU - Horta, N.

AU - Goes, J.

N1 - Instituto de Telecomunicacoes: RAPID UID/EEA/50008/2013 ; FCT-SFRH/BD/103337/2014; SFRH/BPD/104648/2014.

PY - 2017/7/10

Y1 - 2017/7/10

N2 - This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.

AB - This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.

KW - Common-Drain

KW - Common-Source

KW - Design Automation

KW - Digital Filters

KW - Dynamic Amplifier

KW - Energy-Efficiency

KW - High-Speed Low-Power ADC

KW - Switched-Capacitors

KW - Voltage-Combiners

UR - http://www.scopus.com/inward/record.url?scp=85027579238&partnerID=8YFLogxK

U2 - 10.1109/PRIME.2017.7974122

DO - 10.1109/PRIME.2017.7974122

M3 - Conference contribution

AN - SCOPUS:85027579238

SN - 978-1-5090-6508-0

SP - 121

EP - 124

BT - PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017

Y2 - 12 June 2017 through 15 June 2017

ER -

A dynamic voltage-combiners biased OTA for low-power and high-speed SC circuits

Abstract

Conference

Keywords

UN SDGs

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