Abstract
This paper presents the design of a fully-dynamic voltage-combiners biased CMOS operational transconductance amplifier, for low-power high-speed analog-to-digital converters and high-performance switched-capacitor filters, using the UMC 130nm node. The biasing is controlled by switched-capacitors and simulation results of an optimized solution using AIDA-C, a state-of-the-art multi-objective multi-constraint IC optimization tool, present a DC gain of 60.9dB, a gain-bandwidth product of 155.1MHz for a 6pF load and a current consumption of 0.69mArms for a sampling clock frequency of 100MHz.
Original language | English |
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Title of host publication | PRIME 2017 - 13th Conference on PhD Research in Microelectronics and Electronics, Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 121-124 |
Number of pages | 4 |
ISBN (Print) | 978-1-5090-6508-0 |
DOIs | |
Publication status | Published - 10 Jul 2017 |
Event | 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 - Giardini Naxos - Taormina, Italy Duration: 12 Jun 2017 → 15 Jun 2017 |
Conference
Conference | 13th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2017 |
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Country/Territory | Italy |
City | Giardini Naxos - Taormina |
Period | 12/06/17 → 15/06/17 |
Keywords
- Common-Drain
- Common-Source
- Design Automation
- Digital Filters
- Dynamic Amplifier
- Energy-Efficiency
- High-Speed Low-Power ADC
- Switched-Capacitors
- Voltage-Combiners