TY - GEN
T1 - A Comprehensive Study of the Reference Voltage Buffer Design for CR- and CS-Based SAR-ADCs
AU - Viana, Hugo
AU - Barquinha, Pedro
AU - Goes, João
N1 - info:eu-repo/grantAgreement/FCT//2023.00298.BD/PT#
info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/LA%2FP%2F0037%2F2020/PT#
info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDP%2F50025%2F2020/PT#
info:eu-repo/grantAgreement/FCT/6817 - DCRRNI ID/UIDP%2F50025%2F2020/PT#
Funding Information:
This work was supported by the Portuguese National Foundation for Science and Technology (FCT) through the grant 2023.00298.BD, and funded through CTS/00066, LISBOA2030-FEDER-00917900 project no. 14680, LA/P/0037/2020, UIDP/50025/2020 and UIDB/50025/2020.
Publisher Copyright:
© IFIP International Federation for Information Processing 2025.
PY - 2025/6/26
Y1 - 2025/6/26
N2 - Analog-to-digital converters (ADCs) such as successive approximation register (SAR) rely on accurate reference voltage circuits (RVCs) to ensure precise signal conversion. This work examines how charge-redistribution (CR) and charge-sharing (CS) SAR-ADCs impact the design of the buffer, considering different RVC scheme and digital-to-analog converters architectures (DAC). CR-based SAR-ADCs require high-speed buffers due to continuous bit-dependent connections, leading to demanding power and bandwidth requirements. In contrast, CS-based SAR-ADCs, which operate passively during conversion, allow for relaxed buffer design with lower dominant pole frequency and improved power efficiency. Analytical expressions for the reference buffer behavior, including voltage accuracy and settling time, are derived for binary-weighted and C-2C CR- and CS-based SAR ADCs.
AB - Analog-to-digital converters (ADCs) such as successive approximation register (SAR) rely on accurate reference voltage circuits (RVCs) to ensure precise signal conversion. This work examines how charge-redistribution (CR) and charge-sharing (CS) SAR-ADCs impact the design of the buffer, considering different RVC scheme and digital-to-analog converters architectures (DAC). CR-based SAR-ADCs require high-speed buffers due to continuous bit-dependent connections, leading to demanding power and bandwidth requirements. In contrast, CS-based SAR-ADCs, which operate passively during conversion, allow for relaxed buffer design with lower dominant pole frequency and improved power efficiency. Analytical expressions for the reference buffer behavior, including voltage accuracy and settling time, are derived for binary-weighted and C-2C CR- and CS-based SAR ADCs.
KW - CR SAR-ADC
KW - CS SAR-ADC
KW - Reference Buffer
KW - Reference Voltage Circuit
KW - SAR-ADC
UR - https://www.scopus.com/pages/publications/105010030703
U2 - 10.1007/978-3-031-97051-1_27
DO - 10.1007/978-3-031-97051-1_27
M3 - Conference contribution
AN - SCOPUS:105010030703
SN - 9783031970504
T3 - IFIP Advances in Information and Communication Technology
BT - Technological Innovation for AI-Powered Cyber-Physical Systems
A2 - Camarinha-Matos, Luis M.
A2 - Ferrada, Filipa
PB - Springer
T2 - 16th IFIP WG 5.5 / SOCOLNET Advanced Doctoral Conference on Computing, Electrical, and Industrial Systems, DoCEIS 2025
Y2 - 2 July 2025 through 4 July 2025
ER -