TY - JOUR
T1 - A compact model and direct parameters extraction techniques For amorphous gallium-indium-zinc-oxide thin film transistors
AU - Moldovan, Oana
AU - Castro-Carranza, Alejandra
AU - Cerdeira, Antonio
AU - Estrada, Magali
AU - Barquinha, Pedro Miguel Cândido
AU - Martins, Rodrigo
AU - Fortunato, Elvira
AU - Miljakovic, Slobodan
AU - Iñiguez, Benjamin
N1 - Sem PDF.
info:eu-repo/grantAgreement/FCT/5876/147333/PT#
info:eu-repo/grantAgreement/FCT/3599-PPCDT/126341/PT#
Silvaco Inc. (T12129S)
ERDF (European Regional Development Fund) funds through COMPETE 2020 Programme
National Funds through FCT-Portuguese Foundation for Science and Technology
(UID/CTM/50025/2013; EXCL/CTM-NAN/0201/2012)
PY - 2016/12
Y1 - 2016/12
N2 - An advanced compact and analytical drain current model for the amorphous gallium indium zinc oxide (GIZO) thin film transistors (TFTs) is proposed. Its output saturation behavior is improved by introducing a new asymptotic function. All model parameters were extracted using an adapted version of the Universal Method and Extraction Procedure (UMEM) applied for the first time for GIZO devices in a simple and direct form. We demonstrate the correct behavior of the model for negative VDS, a necessity for a complete compact model. In this way we prove the symmetry of source and drain electrodes and extend the range of applications to both signs of VDS. The model, in Verilog-A code, is implemented in Electronic Design Automation (EDA) tools, such as Smart Spice, and compared with measurements of TFTs. It describes accurately the experimental characteristics in the whole range of GIZO TFTs operation, making the model suitable for the design of circuits using these types of devices.
AB - An advanced compact and analytical drain current model for the amorphous gallium indium zinc oxide (GIZO) thin film transistors (TFTs) is proposed. Its output saturation behavior is improved by introducing a new asymptotic function. All model parameters were extracted using an adapted version of the Universal Method and Extraction Procedure (UMEM) applied for the first time for GIZO devices in a simple and direct form. We demonstrate the correct behavior of the model for negative VDS, a necessity for a complete compact model. In this way we prove the symmetry of source and drain electrodes and extend the range of applications to both signs of VDS. The model, in Verilog-A code, is implemented in Electronic Design Automation (EDA) tools, such as Smart Spice, and compared with measurements of TFTs. It describes accurately the experimental characteristics in the whole range of GIZO TFTs operation, making the model suitable for the design of circuits using these types of devices.
KW - Compact modeling
KW - GIZO
KW - TFT transistors
KW - Parameter extraction
UR - http://www.scopus.com/inward/record.url?scp=84994316272&partnerID=8YFLogxK
U2 - 10.1016/j.sse.2016.09.011
DO - 10.1016/j.sse.2016.09.011
M3 - Article
AN - SCOPUS:84994316272
SN - 0038-1101
VL - 126
SP - 81
EP - 86
JO - Solid-State Electronics
JF - Solid-State Electronics
ER -