In the field of radio receivers, downconversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the converter's performance in terms of noise and linearity. As an alternative, we propose a receiver architecture that considers the ADC as both a quantizer and a downconverter block. This is achieved through the use of a variable reference signal (in this case, a voltage), as opposed to classic time-invariant reference signals. When embedded into a charge-sharing (CS) successive approximation register (SAR) ADC, this varying reference voltage is “saved” in the digital-to-analog converter (DAC) capacitor bank during the sampling phase, preventing any conversion errors. Furthermore, a phase-locked loop (PLL) is used in order to provide an on-chip solution for the generation of this variable reference voltage, which also removes the need for dedicated bandgap circuits and reference buffers. Post-layout simulations of an 8-bit 50 MS/s CS-SAR ADC show that the proposed “embedded mixing” technique is able to downconvert a high-frequency signal while also increasing the effective resolution by around 0.5 bits, when compared with a standard DC reference voltage.
|Number of pages||15|
|Journal||International Journal of Circuit Theory and Applications|
|Publication status||Published - 1 Jul 2020|
- analog-to-digital converters
- embedded downconversion
- variable references