This paper describes a switched capacitor, 3rd order MASH 2-1 ΣΔ modulator, for signals with a bandwidth of 20kHz, using passive integrators implemented based on the ultra incomplete settling (UIS) concept. The UIS concept requires RC time constant values much larger than the clock period. Due to the low signal bandwidth the clock frequency is 10 MHz, which would result in large resistors and capacitors that would occupy a large area. The proposed circuit uses monostable circuits to reduce the active time of the clock signals, reducing the area occupied by the resistors and capacitors. Electrical transient noise simulations of the complete ΣΔ circuit show that the modulator achieves a peak SNDR of 92.06 dB, an ENOB of 15 bits and a DR of 111.4 dB for a signal bandwidth of 20 kHz, while dissipating 86 μW from a 1.1 V power supply voltage, resulting in a FOMW of 65.6 fJ/conv.-step and a FOMs of 176 dB.