This paper presents a ΔΣ modulator (ΔΣM) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a ΔΣM using mostly dynamic elements thus reducing the power dissipation. A prototyped 2nd-order ΔΣM circuit, using this technique, was designed in a 130 nm CMOS technology; the measured results prove the validity of the concept. Measured results show that the ΔΣM achieves a peak SNDR of 72.8 dB, a peak SNR of 73.9 dB and a DR of 78.2 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating less than 300 μW from a 1.2V power supply voltage, resulting in a FOM of 139.3 fJ/conv.-step. As far as the authors have knowledge, this circuit represents the first prototyped switched-capacitor (SC) circuit based on UIS.
|Title of host publication||Proceedings of the ESSCIRC (ESSCIRC)|
|Publication status||Published - 1 Jan 2011|
|Event||ESSCIRC (ESSCIRC), 2011 - |
Duration: 1 Jan 2011 → …
|Conference||ESSCIRC (ESSCIRC), 2011|
|Period||1/01/11 → …|
Goes, J. C. D. P., & Paulino, N. F. S. V. (2011). A 1.2 V 300 μW second-order switched-capacitor ΔΣ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS. In Proceedings of the ESSCIRC (ESSCIRC) (pp. 271-274) https://doi.org/10.1109/ESSCIRC.2011.6044959