A 1.2 V 300 μW second-order switched-capacitor ΔΣ modulator using ultra incomplete settling with 73 dB SNDR and 300 kHz BW in 130 nm CMOS

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Abstract

This paper presents a ΔΣ modulator (ΔΣM) circuit based on the implementation of discrete time filters using ultra incomplete settling (UIS). This approach allows building a ΔΣM using mostly dynamic elements thus reducing the power dissipation. A prototyped 2nd-order ΔΣM circuit, using this technique, was designed in a 130 nm CMOS technology; the measured results prove the validity of the concept. Measured results show that the ΔΣM achieves a peak SNDR of 72.8 dB, a peak SNR of 73.9 dB and a DR of 78.2 dB for a signal with a bandwidth (BW) of 300 kHz, while dissipating less than 300 μW from a 1.2V power supply voltage, resulting in a FOM of 139.3 fJ/conv.-step. As far as the authors have knowledge, this circuit represents the first prototyped switched-capacitor (SC) circuit based on UIS.
Original languageUnknown
Title of host publicationProceedings of the ESSCIRC (ESSCIRC)
Pages271-274
ISBN (Electronic)978-1-4577-0702-5
DOIs
Publication statusPublished - 1 Jan 2011
EventESSCIRC (ESSCIRC), 2011 -
Duration: 1 Jan 2011 → …

Conference

ConferenceESSCIRC (ESSCIRC), 2011
Period1/01/11 → …

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