We present a new RC relaxation oscillator with pulse self biasing, to reduce power consumption, and with harmonic filtering and resistor feedback, to reduce phase-noise. A circuit prototype in the hundreds of MHz range, designed in a 130 nm CMOS technology has a very low phase-noise, -132.6 dBc/Hz @ 10 MHz offset, and the power consumption is only 1 mW, which leads to a figure of merit (FOM) of -159.1 dBc/Hz.
|Title of host publication||IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1 Jan 2011|
|Event||2011 IEEE International Symposium on Circuits and Systems (ISCAS) - |
Duration: 1 Jan 2011 → …
|Conference||2011 IEEE International Symposium on Circuits and Systems (ISCAS)|
|Period||1/01/11 → …|