TY - JOUR
T1 - A 0.9-V Programmable Second-Order Bandpass Switched-Capacitor Filter for IoT Applications
AU - Serra, Hugo
AU - Oliveira, João Pedro Abreu de
AU - Paulino, Nuno
N1 - info:eu-repo/grantAgreement/FCT/SFRH/SFRH%2FBD%2F87476%2F2012/PT#
info:eu-repo/grantAgreement/EC/H2020/644852/EU#
sem pdf conforme despacho.
PIDDAC program funds, Project PEST (PEST-OE/EEI/UI0066/2015)
PY - 2018/10
Y1 - 2018/10
N2 - This paper presents a programmable second-order bandpass switched-capacitor filter implemented for an Internet-of-Things water management sensor node. The filter circuit, which is based on the Sallen-Key topology, is implemented using a low-gain amplifier (< 2), avoiding designing high-gain high-bandwidth opamps, which can be difficult to design in advanced CMOS technologies, due to the reduction of the supply voltage and of the intrinsic gain of the transistors. Without the high gain, the circuit becomes sensitive to the effects of parasitic capacitances, which have to be minimized and compensated during the design process. The filter circuit was designed and fabricated in a 130 nm CMOS technology, using a supply voltage of only 0.9 V, to reduce the power dissipation, and a clock frequency of 1 MHz. Measurement results show that the filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. In the default digital control code of the capacitor banks, the circuit has an IM3 of -66.5 dB. The total power consumption is 257 μW.
AB - This paper presents a programmable second-order bandpass switched-capacitor filter implemented for an Internet-of-Things water management sensor node. The filter circuit, which is based on the Sallen-Key topology, is implemented using a low-gain amplifier (< 2), avoiding designing high-gain high-bandwidth opamps, which can be difficult to design in advanced CMOS technologies, due to the reduction of the supply voltage and of the intrinsic gain of the transistors. Without the high gain, the circuit becomes sensitive to the effects of parasitic capacitances, which have to be minimized and compensated during the design process. The filter circuit was designed and fabricated in a 130 nm CMOS technology, using a supply voltage of only 0.9 V, to reduce the power dissipation, and a clock frequency of 1 MHz. Measurement results show that the filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. In the default digital control code of the capacitor banks, the circuit has an IM3 of -66.5 dB. The total power consumption is 257 μW.
KW - Band-pass filters
KW - Biquadratic filter
KW - Capacitance
KW - Capacitors
KW - Clocks
KW - Frequency measurement
KW - low-gain amplifier
KW - Sallen-Key topology
KW - switched-capacitor circuit.
KW - Switches
KW - Transistors
UR - http://www.scopus.com/inward/record.url?scp=85049462442&partnerID=8YFLogxK
U2 - 10.1109/TCSII.2018.2852812
DO - 10.1109/TCSII.2018.2852812
M3 - Article
AN - SCOPUS:85049462442
SN - 1549-7747
VL - 65
SP - 1335
EP - 1339
JO - IEEE Transactions on Circuits and Systems II: Express Briefs
JF - IEEE Transactions on Circuits and Systems II: Express Briefs
IS - 10
ER -