A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW

João L A De Melo; João Carlos da Palma Goes; Nuno Filipe Silva Veríssimo Paulino

doi:10.1109/VLSIC.2015.7231294

A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW

João L A De Melo, João Carlos da Palma Goes, Nuno Filipe Silva Veríssimo Paulino

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

24 Citations (Scopus)

Abstract

A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability, the modulator is optimized using genetic algorithms (GAs). The 65 nm CMOS ΔΣM, occupying only 0.013 mm2, dissipates 256 μW from a 0.7 V supply and achieves a peak SNDR of 69.1 dB with 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a FoMSchreier of 175.1 dB.

Original language	English
Title of host publication	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	C290-C291
ISBN (Print)	978-4-86348-502-0
DOIs	https://doi.org/10.1109/VLSIC.2015.7231294
Publication status	Published - 31 Aug 2015
Event	29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015) - Kyoto, Japan Duration: 17 Jun 2015 → 19 Jun 2015 Conference number: 29th

Conference

Conference	29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015)
Abbreviated title	VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	17/06/15 → 19/06/15

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

Modulation
Gain
CMOS integrated circuits
Very large scale integration
Bandwidth
Resistors
Design methodology

Access to Document

10.1109/VLSIC.2015.7231294Licence: Unspecified

http://ieeexplore.ieee.org/document/7231294/Licence: Unspecified

Cite this

@inproceedings{9db0ffa4263b482dad85b2bfabc1a389,

title = "A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW",

abstract = "A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability, the modulator is optimized using genetic algorithms (GAs). The 65 nm CMOS ΔΣM, occupying only 0.013 mm2, dissipates 256 μW from a 0.7 V supply and achieves a peak SNDR of 69.1 dB with 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a FoMSchreier of 175.1 dB.",

keywords = "Modulation, Gain, CMOS integrated circuits, Very large scale integration , Bandwidth , Resistors, Design methodology",

author = "\{De Melo\}, \{Jo{\~a}o L A\} and Goes, \{Jo{\~a}o Carlos da Palma\} and Paulino, \{Nuno Filipe Silva Ver{\'i}ssimo\}",

note = "Sem PDF. This work was supported by the Portuguese FCT through projects DISRUPTIVE (EXCL/EEI-ELC/0261/2012), PEST (PEST-OE/EEI/UI0066/2015) and also through Ph.D. grant (SFRH/BD/72362/2010); 29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015), VLSI Circuits 2015 ; Conference date: 17-06-2015 Through 19-06-2015",

year = "2015",

month = aug,

day = "31",

doi = "10.1109/VLSIC.2015.7231294",

language = "English",

isbn = " 978-4-86348-502-0",

pages = "C290--C291",

booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

address = "United States",

}

De Melo, JLA, Goes, JCDP & Paulino, NFSV 2015, A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW. in IEEE Symposium on VLSI Circuits, Digest of Technical Papers., 7231294, Institute of Electrical and Electronics Engineers (IEEE), pp. C290-C291, 29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015), Kyoto, Japan, 17/06/15. https://doi.org/10.1109/VLSIC.2015.7231294

A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW. / De Melo, João L A; Goes, João Carlos da Palma ; Paulino, Nuno Filipe Silva Veríssimo.
IEEE Symposium on VLSI Circuits, Digest of Technical Papers. Institute of Electrical and Electronics Engineers (IEEE), 2015. p. C290-C291 7231294.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW

AU - De Melo, João L A

AU - Goes, João Carlos da Palma

AU - Paulino, Nuno Filipe Silva Veríssimo

N1 - Conference code: 29th

PY - 2015/8/31

Y1 - 2015/8/31

N2 - A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability, the modulator is optimized using genetic algorithms (GAs). The 65 nm CMOS ΔΣM, occupying only 0.013 mm2, dissipates 256 μW from a 0.7 V supply and achieves a peak SNDR of 69.1 dB with 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a FoMSchreier of 175.1 dB.

AB - A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability, the modulator is optimized using genetic algorithms (GAs). The 65 nm CMOS ΔΣM, occupying only 0.013 mm2, dissipates 256 μW from a 0.7 V supply and achieves a peak SNDR of 69.1 dB with 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a FoMSchreier of 175.1 dB.

KW - Modulation

KW - Gain

KW - CMOS integrated circuits

KW - Very large scale integration

KW - Bandwidth

KW - Resistors

KW - Design methodology

U2 - 10.1109/VLSIC.2015.7231294

DO - 10.1109/VLSIC.2015.7231294

M3 - Conference contribution

SN - 978-4-86348-502-0

SP - C290-C291

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers (IEEE)

T2 - 29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015)

Y2 - 17 June 2015 through 19 June 2015

ER -

A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW

Abstract

Conference

UN SDGs

Keywords

Access to Document

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