A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW

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Abstract

A continuous-time (CT) delta-sigma modulator (ΔΣM), with 27.5 fJ/conv.-step energy efficiency, employing passive RC integrators is proposed. A simple differential pair is incorporated in the loop-filter between each passive RC integrator and, the extra required gain in the loop is obtained in the comparator. Due to the many design issues, such as the trade-off between RC variations and loop stability, the modulator is optimized using genetic algorithms (GAs). The 65 nm CMOS ΔΣM, occupying only 0.013 mm2, dissipates 256 μW from a 0.7 V supply and achieves a peak SNDR of 69.1 dB with 2 MHz bandwidth (BW). The dynamic range (DR) reaches 76.2 dB, which corresponds to a FoMSchreier of 175.1 dB.
Original languageEnglish
Title of host publicationIEEE Symposium on VLSI Circuits, Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
PagesC290-C291
ISBN (Print) 978-4-86348-502-0
DOIs
Publication statusPublished - 31 Aug 2015
Event29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015) - Kyoto, Japan
Duration: 17 Jun 201519 Jun 2015
Conference number: 29th

Conference

Conference29th Annual Symposium on VLSI Circuits (VLSI Circuits 2015)
Abbreviated titleVLSI Circuits 2015
CountryJapan
CityKyoto
Period17/06/1519/06/15

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Keywords

  • Modulation
  • Gain
  • CMOS integrated circuits
  • Very large scale integration
  • Bandwidth
  • Resistors
  • Design methodology

Cite this

De Melo, J. L. A., Goes, J. C. D. P., & Paulino, N. F. S. V. (2015). A 0.7 V 256 μW ΔΣ modulator with passive RC integrators achieving 76 dB DR in 2 MHz BW. In IEEE Symposium on VLSI Circuits, Digest of Technical Papers (pp. C290-C291). [7231294] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231294