A 0.5 V Ultra-low Power Quadrature Ring Oscillator

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper we present a CMOS quadrature ring oscillator operating at 0.5 V. Due to this very low voltage conditions, new project technique using the available terminal of the transistors (bulk) is used in order to reduce the threshold voltage of the transistors, thus improving the voltage headroom. The technique is applied in a conventional inverter-based ring oscillator with a feedback topology capable to generate quadrature signals. Simulations results in a 130 nm CMOS technology shows that a very simple VCO in the GHz range can be obtained, by changing the bulk voltage of transistors (NMOS or PMOS). The circuit operates with less than 50μW achieving a FoM of about -115 dBc/Hz at 10 MHz offset.
Original languageEnglish
Title of host publicationIFIP Advances in Information and Communication Technology
Pages575-581
Volume423
ISBN (Electronic)978-3-642-54734-8
DOIs
Publication statusPublished - 2014
Event5th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2014 -
Duration: 1 Jan 2014 → …

Conference

Conference5th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems, DoCEIS 2014
Period1/01/14 → …

Keywords

  • CMOS circuit
  • Low voltage
  • Quadrature RC oscillator
  • Ultra-low power

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  • Cite this

    Eusébio, J., Oliveira, L. A. B. G. D., Pires, L. M., & Oliveira, J. P. A. D. (2014). A 0.5 V Ultra-low Power Quadrature Ring Oscillator. In IFIP Advances in Information and Communication Technology (Vol. 423, pp. 575-581) https://doi.org/10.1007/978-3-642-54734-8_64