Abstract
In this paper we present a CMOS quadrature ring oscillator operating at 0.5 V. Due to this very low voltage conditions, new project technique using the available terminal of the transistors (bulk) is used in order to reduce the threshold voltage of the transistors, thus improving the voltage headroom. The technique is applied in a conventional inverter-based ring oscillator with a feedback topology capable to generate quadrature signals. Simulations results in a 130 nm CMOS technology shows that a very simple VCO in the GHz range can be obtained, by changing the bulk voltage of transistors (NMOS or PMOS). The circuit operates with less than 50μW achieving a FoM of about -115 dBc/Hz at 10 MHz offset.
Original language | English |
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Title of host publication | IFIP Advances in Information and Communication Technology |
Pages | 575-581 |
Volume | 423 |
ISBN (Electronic) | 978-3-642-54734-8 |
DOIs | |
Publication status | Published - 2014 |
Event | 5th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS) - Costa da Caparica, Portugal Duration: 7 Apr 2014 → 9 Apr 2014 |
Conference
Conference | 5th IFIP WG 5.5/SOCOLNET Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS) |
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Country/Territory | Portugal |
City | Costa da Caparica |
Period | 7/04/14 → 9/04/14 |
Keywords
- CMOS circuit
- Low voltage
- Quadrature RC oscillator
- Ultra-low power