@inproceedings{0132af4082db44a08798b6ab3ec02fdb,
title = "15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM",
abstract = "ΔΣM performance can be improved by using MASH or SMASH structures to obtain higher-order noise shaping [1]. They have better stability than single-loop structures. The power dissipation of ΔΣMs can be reduced by using simpler amplifiers such as single-stage or inverter-based amplifiers [2]. Selecting a passive or active-passive ΔΣM architecture, where the processing gain of comparator is used in the feedback loop of the ΔΣM's filter [3], allows a reduction in the number of amplifiers and their gain. This solution is very appealing for deep-nanometer CMOS technologies, because a comparator can achieve large gain through positive feedback, which improves with faster transistors. This paper presents a passive-active CT 2-1 MASH ΔΣM using RC integrators, low-gain stages (∼20dB) and simplified digital cancellation logic (DCL). The ΔΣM, clocked at 1GHz, achieves DR/SNR/SNDR of 77/76/72.2dB for input signal BW of 10MHz, while dissipating 1.57mW from a 1V supply.",
keywords = "Feedback amplifiers",
author = "Blazej Nowacki and Nuno Paulino and Joao Goes",
year = "2016",
month = "2",
day = "23",
doi = "10.1109/ISSCC.2016.7418013",
language = "English",
isbn = "978-1-4673-9466-6",
series = "IEEE International Solid State Circuits Conference",
publisher = "IEEE",
pages = "274--275",
editor = "Fujino, {Laura C.}",
booktitle = "2016 IEEE International Solid-State Circuits Conference (ISSCC 2016)",
}