15.3 A 1V 77dB-DR 72dB-SNDR 10MHz-BW 2-1 MASH CT ΔΣM

Blazej Nowacki, Nuno Paulino, Joao Goes

Research output: Chapter in Book/Report/Conference proceedingConference contribution

26 Citations (Scopus)

Abstract

ΔΣM performance can be improved by using MASH or SMASH structures to obtain higher-order noise shaping [1]. They have better stability than single-loop structures. The power dissipation of ΔΣMs can be reduced by using simpler amplifiers such as single-stage or inverter-based amplifiers [2]. Selecting a passive or active-passive ΔΣM architecture, where the processing gain of comparator is used in the feedback loop of the ΔΣM's filter [3], allows a reduction in the number of amplifiers and their gain. This solution is very appealing for deep-nanometer CMOS technologies, because a comparator can achieve large gain through positive feedback, which improves with faster transistors. This paper presents a passive-active CT 2-1 MASH ΔΣM using RC integrators, low-gain stages (∼20dB) and simplified digital cancellation logic (DCL). The ΔΣM, clocked at 1GHz, achieves DR/SNR/SNDR of 77/76/72.2dB for input signal BW of 10MHz, while dissipating 1.57mW from a 1V supply.

Original languageEnglish
Title of host publication2016 IEEE International Solid-State Circuits Conference (ISSCC 2016)
EditorsLaura C. Fujino
Place of PublicationNew York, USA
PublisherIEEE
Pages274-275
Number of pages2
ISBN (Electronic)978-1-4673-9467-3
ISBN (Print)978-1-4673-9466-6
DOIs
Publication statusPublished - 23 Feb 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: 31 Jan 20164 Feb 2016

Publication series

NameIEEE International Solid State Circuits Conference
PublisherIEEE
Volume59
ISSN (Print)0193-6530

Conference

Conference63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period31/01/164/02/16

Keywords

  • Feedback amplifiers

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